Electronic design automation (EDA) is a general term used to describe computer-based design tools that assist an engineer or designer in their design tasks. EDA tools are especially useful in the integrated circuit (IC) design field. The improvement of EDA tools for IC design work has enabled a corresponding increase in speed to market for electronic products and facilitated a greater level of sophisticated interoperability between systems used by disparate designers and manufacturers.
EDA tools often involve circuit schematic capture, design verification and circuit layout for IC circuit design in the analog, digital, mixed signal, and custom circuit devices fields. With the layout aspect of EDA work, IC designers continue to strive towards more efficient use of a device's physical space. Manual and automated layout tools within conventional EDA tools commonly assist IC designers in this manner. In doing so, the EDA tools rely upon design rules that provide working parameters for an acceptable design and that can be verified for a particular design.
As technology advances, the details and complexity of design rules are commonly known to increase at a rapid pace. IC layout typically follows semiconductor foundry design rules for a particular process that will implement the designed IC (e.g., a 65 nm process). Following such design rules helps to ensure the yield rate at manufacturing. When design rules are found to be in violation by a particular design, an EDA tool user typically uses one or more aspects or features of the EDA tool to fix or otherwise change the current design to remove the design rule violations. However, at times, this can be cumbersome and quite complicated as what may appear at first to be a desired fix for a detected DRC error or violation may actually introduce or induce other errors or violations. Additionally, some errors may be multi-faceted in that a given layout may violate several rules in several different ways. Thus, there is a need to easily detect and implement fixes to remove verification rule violations without causing or while minimizing new violations and to handle more complex verification rule violations.